1. Field of the Invention
The present invention relates to a buried channel type transistor having a trench gate and a method of manufacturing the buried channel type transistor. More particularly, the present invention relates to a buried channel type transistor having a trench gate, and a method of manufacturing the buried channel type transistor.
2. Description of the Related Art
As semiconductor devices are highly integrated, sizes of active regions on which MOS transistor are formed may be greatly reduced. Thus, the MOS transistor formed in the active region has a channel length well below a micrometer (μm). When the MOS transistor has a reduced channel length, a source and a drain of the transistor may strongly affect an electric field or a voltage of the channel region. This affect is referred to as “short channel effect.” For example, the short channel effect includes the decrease of a threshold voltage (Vth) of the gate electrode. The threshold voltage decrease of the gate electrode may be generated in accordance with the reduction of the length of the channel region because the channel region may be greatly affected by the voltage of the gate as well as charges, electric fields or voltage distribution in the depletion layers of the source/drain regions. The short channel effect additionally includes the decrease of a breakdown voltage between the source/drain regions. The depletion layer of the drain region increases in proportion to the increase of the voltage of the drain region. When the gate has greatly reduced length, the depletion layer of the drain region may contact the depletion layer of the source region. In this state, the electric field of the drain region may affect on the source region so that the diffusion voltage near the source region may be reduced. As a result, a current may flow between the source region and the drain region without the formation of the channel region. This phenomenon is referred to as “punch-through.” When punch-through occurs, the current of the drain region may be rapidly increased at a saturation region.
In the meantime, a conventional MOS transistor includes a gate electrode formed using an N type polysilicon layer in which impurities such as phosphorus (P) are heavily implanted. Although a recent MOS transistor has a polycide structure of metal silicide and polysilicon, the MOS transistor includes an N type polysilicon layer that directly contacts a gate oxide layer formed on a substrate. When an N-MOS transistor includes the above-mentioned gate electrode, a threshold voltage of the gate electrode may be reduced because the difference of work functions between the N type polysilicon layer and a P-type semiconductor substrate is relative large. To solve this problem, P type impurities may be generally implanted into a channel region of the N-MOS transistor.
On the other hand, when an N+ type polysilicon layer is used as a gate electrode of a P-MOS transistor, a threshold voltage of the gate electrode may have negative value because of the difference between work functions of the N+ type polysilicon layer and the N type semiconductor substrate. In order to adjust an absolute value of the threshold voltage of the P-MOS transistor to be substantially identical to that of the N-MOS transistor, impurities opposite to those of the substrate may be implanted into the channel region of the P-MOS transistor, thereby reducing the absolute value of the threshold voltage of the P-MOS transistor. As a result, a very shallow p-n junction may be formed in the channel region of the P-MOS transistor including the N type polysilicon layer as the gate electrode, thereby forming a buried channel type P-MOS transistor. The very shallow p-n junction, however, may also be formed in the channel region of the N-MOS transistor including the N type polysilicon layer as the gate electrode, thereby forming a surface channel type N-MOS transistor.
The buried channel type P-MOS transistor has advantages in that carriers in the channel region may not be affected by surface scattering, and the mobility of the carriers may be increased. It, however, has disadvantages in that a gate voltage of the buried channel type P-MOS transistor may be decreased and a short channel effect may easily occur in the buried channel type P-MOS transistor because a p-n junction is not formed near a boundary between a silicon substrate. Furthermore, a gate oxide layer and a drain voltage may strongly affect the channel region. To lessen the above-mentioned problems, a stopper is formed beneath the channel region of the buried channel type P-MOS transistor to reduce the short channel effect.
FIG. 1 is a cross-sectional view illustrating a conventional buried channel type P-MOS transistor having a plan structure.
Referring to FIG. 1, a P type well (not shown) and an N type well 12 are formed in a P type semiconductor substrate 10. An N-MOS transistor is formed on the P type well, whereas a P-MOS transistor is formed on the N type well 12 to independently optimize the N-MOS transistor and the P-MOS transistor.
P type impurities such as boron (B) generated from boron bifluoride (BF2) are implanted into a channel region of the substrate 10 so as to form a threshold voltage control region 16 that adjusts a threshold voltage of the P-MOS transistor to be substantially identical to that of the N-MOS transistor.
A stopper 14 is formed by heavily implanting N type impurities such as arsenic (As) into a portion of the substrate 10 beneath the channel region. The stopper 14 prevents surface depletion of the threshold voltage control region 16. The stopper 14 has a high impurity concentration, which reduces punch-through by preventing a current of a drain from permeating into the channel region and a source region.
After a gate insulation layer 18 is formed on the substrate 10, a gate electrode 20 is formed on the gate insulation layer 18 using N type polysilicon. Here, the N-MOS and the P-MOS transistors have the N type gate electrodes 20.
A gate spacer 22 is formed on a sidewall of the gate electrode 20 using silicon oxide.
N+ type source/drain regions are formed in a portion of the P type well adjacent to the gate electrode 20 using N type impurities such as arsenic, whereas P+type source/drain regions 24 are formed in a portion of the N well 12 adjacent to the gate electrode 20 using P type impurities such as boron.
In the conventional buried channel type P-MOS transistor, in order to reduce a short channel effect, the stopper 14 is formed beneath the channel region or a junction depth of the source/drain regions is decreased.
Meanwhile, a highly integrated semiconductor device includes a dual gate structure in which an N-MOS transistor has an N type polysilicon gate and a P-MOS transistor has a P type polysilicon gate to reduce a short channel effect of the P-MOS transistor. However, manufacturing processes for the dual gate structure may be complicated and manufacturing cost for forming the dual gate structure may be greatly increased because the N-MOS transistor and the P-MOS transistor are separately formed using additional photo masks and additional photolithography processes.
Recently, several vertical type MOS transistors having trench gate electrodes have been disclosed in U.S. Laid Open Patent Publication No. 2002-38886, U.S. Pat. No. 6,316,806 and Japanese Laid Open Patent Publication No. 2001-339063. The MOS transistor having the trench gate electrode may have a sufficient breakdown voltage between source/drain regions thereof, and may reduce a short channel effect because a recess type channel thereof may augment a length of a channel. However, these conventional MOS transistors with trench gate electrodes includes a surface channel region only. Thus, there is still a requirement to develop a buried channel type P-MOS transistor that includes an N type polysilicon gate electrode in a trench.
Embodiments of the invention address these and other disadvantages of the conventional art.